Field of Invention
Embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional (3-D) semiconductor device including pad structures and a method of manufacturing the same.
Description of the Related Art
A nonvolatile memory device retains stored data although the supply of power to the device may be cut-off. As the degree of integration of 2-D structured memory devices including memory cells fabricated on a single layer of a silicon substrate is approaching a limit, a 3-D structured nonvolatile memory device has been proposed. The 3-D nonvolatile memory device typically includes memory cells that are vertically stacked on a silicon substrate.
In this 3-D nonvolatile memory device, desired memory cells are driven by supplying biases to respective word lines stacked in multiple layers over a substrate. To drive memory cells by supplying biases to respective word lines, a pad unit is formed for each word line by patterning the word lines, formed in a slimming region, in a step form. Furthermore, contact plugs and metal lines coupled to the respective word lines are formed so that the word lines stacked in multiple layers may be controlled.
FIG. 1 is a perspective view showing a structure of a known 3-D nonvolatile memory device. For ease of description, only a cell structure and pad structures are illustrated in FIG. 1.
As shown in FIG. 1, the known 3-D nonvolatile memory device includes a cell region CR and first and second slimming regions SR1 and SR2 placed on both sides of the cell region CR.
The cell structure C placed in the cell region CR includes channel layers CH configured to penetrate the cell structure C in a stack direction.
Pad structures P1 and P2 are formed in the slimming regions SR1 and SR2. Each of the pad structures P1 and P2 includes a step form in which one layer forms one stage. In order to form these pad structures, after forming word lines stacked in multiple layers, an etch process is repeatedly performed while reducing one mask pattern.
In a structure, such as that described above, the pad structures P1 and P2 are formed in a step form in which one layer forms one stage. Accordingly, the slimming regions SR1 and SR2 become wide, and an improvement in the degree of integration of memory devices is limited. Furthermore, in order to form n layers of the pad structures P1 and P2 in a step form, n etch processes must be performed, thereby increasing the complexity of the etching process.